A linear voltage regulator may typically be used with portable battery-powered devices, e.g. cellular telephones. Typical requirements for such regulators are a high PSRR (Power Source Rejection Ratio), very fast response to load transients, low voltage drop, and above all low current consumption, so that the battery charge may last longer.
Such a linear regulator is currently typically implemented with an N-channel MOS power transistor. The adoption of an N-channel transistor is prompted since, for the same performance level, it allows optimum utilization of the silicon area. It also permits a reduction of at least one order of magnitude in the value of the output capacitor.
An exemplary application of a voltage regulator according to the prior art is shown in FIG. 1. A low-drop type of regulator with an N-channel topology, as is shown in FIG. 1, requires that a driving circuit OP be supplied a higher voltage VCP than the power supply voltage VBAT which can be delivered. This higher voltage, in the state-of-art, is provided by a charge pump circuit 2.
The operation of the circuit of FIG. 1 will now be described in detail. The current consumption of the regulator can be calculated by adding together the current I.sub.res flowing through the divider R1-R2 and the current I.sub.op drawn by the driving circuit OP for the power transistor M1. Since the charge pump circuit 2 used for powering the driving circuit OP is a by-n multiplier of the input voltage VBAT, its current draw on the battery will be n times the current I.sub.op that it supplies to the driving circuit OP.
When the efficiency E.sub.FF Of the charge pump circuit is also taken into account, the overall current draw of the regulator on the battery is given as: EQU I.sub.REG =(n/E.sub.FF)*I.sub.OP +I.sub.res.
The compensation employed with a regulator with this topology usually is of the pole-zero type, wherein the internal zero is to cancel out the pole introduced by the load capacitor. The outcome of such compensation is that a dominant pole is created, which greatly slows down the response to load transients and undermines performance in terms of power source rejection.
A known approach to address this problem includes increasing the bias current I.sub.op of the differential stage in the driving circuit OP with a consequent increase in the regulator overall consumption. However, this prior approach clashes with the basic requirement for battery-powered devices having the lowest possible current consumption.